History effect in SOI circuits can lead to less-than-optimal delay-vs.-power circuits due to elevated stimulated leakage and worst-case-history timing for applications. More specifically, Partially-Depleted Silicon On Insulator (PDSOI) technology features a “floating body'” which can be described as a region of silicon beneath the FET channel which is undepleted of its equilibrium carrier concentration, and is largely electrically neutral. This floating body will vary in electric potential (voltage) with use of the transistor.
There are two types of effects that determine the body potential, namely leakage sources, which are static in nature, and capacitive coupling, which is intrinsically transient in its influence on body voltage. The two effects taken with the recent electrical states of a PDSOI FET determine the body voltage.
As the body voltage varies, the FET threshold-voltage (Vt), and hence, the drive currents are influenced. The final outcome of such variations is that the detailed performance of a circuit employing PDSOI will be a function of the most-recent history of use of the circuit. For example, if the circuit has been inactive for some time greater than the relaxation times of the FETs, then the performance will be characteristic of that obtained with body voltages at equilibrium. This is the so-called first-switch state.
By contrast, if the same circuit is stimulated a short-time after the “first-switch” event (i.e., a time significantly less than the relaxation times of the FET body voltage), the body voltages will have been perturbed from the equilibrium values by capacitive coupling from source, drain, and gate, to the body. This will result in a different set of body voltages and, hence, a different, “second-switch,” performance will be characteristic of the circuit.
Using the first and second switch events, the history can be defined as:History=[T1−T2]/[(½)*(T1+T2)]where T1=1st switch delay and T2=2nd switch delay. And, the gate-to-body leakage can affect history in two ways:                1. For T1, the load device has its 1st-switch Vt lowered (closer to zero) which causes the load FET to buck the transition more effectively and hence increase the value of T1; and        2. In the second switch, the body of the load device is unaffected, while the active device now has a more forward-biased body, and hence is faster.        
Thus the second switch becomes faster with increasing gate-to-body leakage, so the net is that history becomes more positive.
However, to minimize variability, and to maximize switching speed per unit power, it is desirable to minimize history, i.e., History=0. To do this, current technology optimizes the circuit by minimizing history, averaged over typical use conditions. But differing history behavior by circuit topology (e.g., inverter, vs. nand, nor, pass-gate, etc.) has left a wide range of history-effect within a real product.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.